This post covers introduction to layout design rules. Layout design rules are introduced in order to create reliable and functional circuits on a small area. Main terms in design rules are feature size (width), separation and overlap. Design rules does represent geometric limitations for for an engineer to create correct topology and geometry of the design.
Design rules are based on MOSIS rules. The main term of MOSIS rules is parameter .
There is several levels of design rules:
- well rules;
- transistor rules;
- contact rules;
- metal rules;
- via rules;
- other rules.
Layout design rules: Well rules
- N-well is deeper mounted than any other transistor implants. Clearance between n-well edges and n+ diffusion should be good enough.
- This clearance is usually determined by the oxide transition time across the well boundary.
- The other rule is grounding n-well, providing sufficient number of well taps. This will prevent significant voltage drops due to well current.
Layout design rules: Transistor rules
transistor is designed with at least for masks:
- active mask – defines where p- or n-diffusion type or gates will be placed;
- n-implant mask – defines areas where n-type diffusion is required; n-type diffusion in p-wells define nMOS transistors; p-type diffusion in n-wells defines pMOS transistors;
- p-implant mask – defines where p-type diffusion is required;p-type diffusion in n-wells define n-type contacts.; p-type diffusion in p-wells define p-well contacts
- polysilicon mask – crossing of polysilicon and diffusion mask defines the gates of transistor.
Polysilicon mask should cover active mask and extend beyond that area, otherwise transistor will be shorted with the diffusion path between source and drain. Crossing of polisilicon and active mask create gate of transistors. Polysilicon and active masks that does not form a transistor should be kept separately.
Layout design rules: Contacts rules
Types of contacts:
- metal to p-active (p-diffusion)
- metal to n-active (n-diffusion)
- metal to polysilicon
- metal to well or substrate
Metal spacing can be different depending on the metal line. But there is certain width applied to small and thick wires. So if there is a need of wider wires, they can be made of several small wires connected together. Spacing rules can be applied to a long parallel wires.
Via (vertical interconnect access) rules
Modern planar technology allows stacked vias.
Usually ready chip is marked with scribe lines, where it should be cut. Manufacturer define the construction of the scribe line.
Alignment mark is placed on the mask to align one mask to another.
Critical dimension test structures are measured after processing to check proper etching of narrow polysilicon or metal lines.
Vernier structures are used to check alignment between layers.
MOSIS scalable design rules
MOSIS CMOS design rules are -scallable. MOSIS CMOS design rules also include SCMOS, SUBM and DEEP rules variations. For example for SUBM rule .
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