Digital systems and design

# Propagation delay in logic gates This post answers the question “What is propagation delay in logic gates?”. Effects happening in the RC circuits are the source of the propagation delay in digital circuits.

Let’s consider two inverters in series as depicted below.

In case of input step function, the voltage waveform at the output of the first MOSFET is depicted below. In order for signal get from $0$ state to $1$ state, there is a time interval ${t}_{0\to 1}$, and then after the signal changes from the state $1$ to $0$, it happens within the time interval ${t}_{1\to 0}$.

Generally speaking the parameters ${t}_{1\to 0}$ and ${t}_{0\to 1}$ are called propagation delay of an inverter for the state $1\to 0$ or $0\to 1$. These two delays are not always equal to each other, so for simplicity the propagation delay is usually chosen the biggest of them .

Lets consider general case of combinational digital circuit with multiple inputs and outputs. We can apply the terms of propagation delays mentioned above as follows:

${t}_{1\to 0}$ is the signal propagation delay for selected input and output terminal for high to low instantaneous transition at the input.

${t}_{0\to 1}$ is the signal propagation delay for selected input and output terminal for low to high instantaneous transition at the input.

So signal propagation delay ${t}_{pd}$ for selected input-output terminals of combinational circuit is .

The output of combinational circuit is characterised with rise and fall times. Rise time of the output is the delay in rising from the lowest value valid high level of the signal at the output. Fall time of the output is the delay in falling from the highest value to the valid low value  at the output.

It’s important to remember that the propagation delay and the rise/fall times are not equal.

Normally digital devices should interpret correctly voltages that belongs to the valid input thresholds, resulting the output values that belong to the valid output range. Due to RC effects the transition on the output goes slower.

Let’s get back again to the series connection of two inverters, presented in SRC model on the figure below. For the case of high input the first circuit works, for the case of low input the second circuit works.

In order to calculate the magnitude of the propagation delay of MOSFET, we must consider it’s SRC model. Getting back to two inverters connected in series, that can be represented as depicted below. When the ${v}_{in1}$ signal is high, then SRC circuit model looks as depicted below. Here the second capacitor ${C}_{GS2}$ is an open circuit.  When ${v}_{in1}$ signal is low, then SRC circuit model looks as depicted below. Here the second capacitor  ${C}_{GS2}$ is charging. Let’s write down KCL for the circuit $\frac{{V}_{C}–{V}_{S}}{{R}_{L}}+{C}_{GS2}\frac{d{v}_{C}}{dt}=0$ so ${v}_{S}+{C}_{GS2}{R}_{L}\frac{d{v}_{C}}{dt}={v}_{S}$. The solution of this differential equation is the sum of homogeneous and particular solutions ${v}_{C}\left(t\right)={v}_{S}+\left({v}_{S}\left(0\right)–{v}_{S}\right){e}^{–\frac{t}{{R}_{L}{C}_{GS2}}}$.

When ${v}_{in1}$ signal is high, then SRC circuit model looks as depicted below. Here the second capacitor ${C}_{GS2}$   is discharging. In accordance to Thenevin transformation we have ${R}_{TH}=\frac{{R}_{L}{R}_{on}}{{R}_{L}+{R}_{on}}$ and ${V}_{TH}=\frac{{V}_{S}{R}_{on}}{{R}_{on}+{R}_{L}}$.

Building a KCL for the last circuit we are having a differential equation $\frac{{V}_{C}–{V}_{TH}}{{R}_{TH}}+{C}_{GS2}\frac{d{V}_{C}}{dt}=0$ so ${V}_{C}+{C}_{GS2}{R}_{TH}\frac{d{V}_{C}}{dt}={V}_{TH}$.

The total solution of this differential equation is the sum homogeneous and particular solutions and we have ${v}_{C}\left(t\right)={V}_{TH}+\left({V}_{S}–{V}_{TH}\right){e}^{–\frac{t}{{R}_{TH}{C}_{GS2}}}$.

The following parameters  are known constants, calculating  $t$  for different levels of ${v}_{C}$ we can find  ${t}_{0\to 1}$ and ${t}_{1\to 0}$ delays, that will allow us to calculate the propagation delay .

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