Digital systems and design

# Static induction transistor construction

This posts tells about static induction transistor construction. Invented by J. Nishizawa in 1975, the static induction devices were first successfully fabricated in Japan. Among the static induction devices, a static induction transistor (SIT) is regarded as a JFET device conducting in the pre-punch-through region.

Static Induction Devices (SID) are a static induction family that includes static induction transistor (SIT), static induction thyristor, static induction diode (SID), static induction transistor logic (SITL), space charge limiting load (SCLL), and static induction MOS transistor (SIMOS). The static induction devices are current-controlled devices by both potential barrier and space charge.

Static induction transistors are characterised with the following features:

• Feature outstanding operating qualities
• Have frequencies up to 1THz
• Belong to great switching speed
• Low switching energy
• Large reverse voltage
• Low forward voltage drop features

SIT is shown schematically on figure 1. The working process of a SIT is that SIT electrostatically instigates a potential interruption in the device as well as maintains the electricity between the drain and source.

In a SIT, where the mall electrostatic field prevails in the region of the potential interruption, the current flow and diffusion through the device can be explained with the following formula ${J}_{n}=\frac{q{D}_{n}{N}_{s}}{{\int }_{{x}_{1}}^{{x}_{2}}exp\left(–\phi \left(x\right)}{{V}_{t}}\right)dx}$, here ${N}_{s}$ is the carrier  concentration for ${x}_{1}$.

The potential can be explained comparatively with the function of the second-order along with the static induction transistor channel and across the transistor channel by the formulas $\phi \left(x\right)=\varphi \left(1–{\left(2\frac{x}{L}–1\right)}^{2}\right)$ and $\phi \left(x\right)=\varphi \left(1–{\left(2\frac{y}{W}–1\right)}^{2}\right)$

are for two-channel dimensions, where $\varphi$ is thought as the height of the potential interruption.

The drain current through the transistor is ${l}_{D}=d{D}_{p}{N}_{s}Z\frac{W}{L}exp\left(\frac{\varphi }{{V}_{T}}\right)$, where ${N}_{s}$ is thought as the concentration of the source,  and  $\frac{W}{L}$are thought as the geometrical properties of the potential saddle of the interruption. Here $\varphi$ is always considered as a function of the gate and drain voltages.

SIT features a low forward voltage drop and can be created by lessening the emitter to the gate of the SIT that’s exposed on the figure below.