Static Induction devices and their features

This post answers the question what are static induction devices and what are their features. Static Induction Devices (SID) are a static induction family that includes static induction transistor (SIT), static induction thyristor, static induction diode (SID), static induction transistor logic (SITL), space charge limiting load (SCLL), and static induction MOS transistor (SIMOS). The static induction devices are current-controlled devices by both potential barrier and space charge.

Invented by J. Nishizawa in 1975, the static induction devices were first successfully fabricated in Japan. Among the static induction devices, a static induction transistor (SIT) is regarded as a JFET (short channel junction field-effect transistor)device conducting in the pre-punch-through region. 

Following are the main features of Static Induction Devices are capability to hold frequencies up to 1THz, outstanding operating qualities, low switching energy, large reverse voltage, low forward voltage drop and some others.

Static induction transistor (SIT) is described on the diagram on the figure below. The working process of a SID is that SID electrostatically instigates a potential interruption in the device as well as maintains the electricity between the drain and source.

In a SID, where the small electrostatic field prevails in the region of the potential interruption, the current flow and diffusion through the device can be explained as: $J_n=\frac{q{D}_n{N}_s}{{\int }_{x_1}^{x_2}exp(–{\displaystyle \frac{\varphi \left(x\right)}{V_t}})dx}$, where $N_s$ is a career concentration for $x_1$.

The potential can be explained comparatively with the function of the second-order along with the static induction transistor channel and across the transistor channel as: $\phi \left(x\right)=F\left(1–{(2\frac{x}{L}–1)}^2\right)$ and $\phi \left(x\right)=F(1–{(2\frac{y}{W}–1)}^2)$ are

or two-channel dimensions, where $F$ is thought as the height of the potential interruption.

The drain current through the transistor is $I_d=d{D}_p{N}_{s}Z\frac{W}{L}exp\left(\frac{F}{V_t}\right)$, where  $N_s$ is thought as the concentration of the source,  and  $\frac{W}{L}$ are thought as the geometrical properties of the potential saddle of the interruption. Here $F$ is always considered as a function of the gate and drain voltages.

Static induction transistors can be used to attain the SID. These diodes feature a low forward voltage drop and can be created by lessening the emitter to the gate of the SIT that’s presented below.