How to calculate the delay in VLSI design using RC representation

This post tells about how to calculate the delay in VLSI design using RC representation, including the term of transfer function.

Let’s consider the circuit depicted below. This is RC model of inverter.

 

Let’s consider transfer function for the circuit. Transfer function describes behaviour of the output signal, depending on the input signal. Transfer function for this circuit is $H\left(s\right)=\frac{1}{1+sRC}$, step response is $V_{out}=V_{DD}{e}^{–\frac{t}{RC}}$. Here $\tau =RC$ is a delay.

Let’s consider NAND gate (second-order system) below.

 

The transfer function here is $H\left(s\right)=\frac{1}{1+s(R_1{C}_1+R_1{C}_2+R_2{C}_2) +s^2{R}_1{C}_1{R}_2{C}_2}$. The step-response here is  $V_{out}\left(t\right)=V_{DD}\frac{n_1{e}^{–{\displaystyle \frac{t}{n_1}}}–n_2{e}^{–{\displaystyle \frac{t}{n_2}}}}{n_1–n_2}$, here $n_{1,2}=\frac{R_1{C}_1+C_2(R_1+R_2)}{2}(1\pm \sqrt{1–\frac{4{\displaystyle \frac{R_2}{R_1}}{\displaystyle \frac{C_2}{C_1}}}{(1+{(1+{\displaystyle \frac{R_2}{R_1}}){\displaystyle \frac{C_2}{C_1}})}^2}})$. Here $\tau =R_1{C}_1+(R_1+R_2)C_2$ is a delay.

Most of the circuits can be represented as a tree of RC circuits with the voltage source root. So we can conclude that delay in a general circuit is $\tau =\sum _i{R}_{in}{C}_i$.

Let’s calculate the delay for an inverter driving n identical load inverters like on the drawing below.

Here load is represented by capacitance $3nC$, driving inverter is represented by the capacitance $3C$. Then the total capacitance is $3C(1+n)$, and the delay is $\tau =3RC(1+n)$.

Usually it is comfortable to speak about delay in the non-process related terms normalising the delay to parasitic capacitance $3RC$, so we have $t_{delay}=\frac{\tau }{3RC}$.

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