VLSI Design

How to calculate the delay in VLSI design using RC representation

How to calculate the delay in VLSI design using RC representation

This post tells about how to calculate the delay in VLSI design using RC representation, including the term of transfer function.

Let’s consider the circuit depicted below. This is RC model of inverter.

How to calculate the delay in VLSI design using RC representation
RC representation of inverter
Inverter circuit

 

Let’s consider transfer function for the circuit. Transfer function describes behaviour of the output signal, depending on the input signal. Transfer function for this circuit is H(s)=11+sRC, step response is Vout=VDDetRC. Here τ=RC is a delay.

Let’s consider NAND gate (second-order system) below.

 

How to calculate the delay in VLSI design using RC representation
NAND RC representation
NAND circuit

The transfer function here is H(s)=11+s(R1C1+R1C2+R2C2) +s2R1C1R2C2. The step-response here is  Vout(t)=VDDn1etn1n2etn2n1n2, here n1,2=R1C1+C2(R1+R2)2(1±14R2R1C2C1(1+(1+R2R1)C2C1)2). Here τ=R1C1+(R1+R2)C2 is a delay.

Most of the circuits can be represented as a tree of RC circuits with the voltage source root. So we can conclude that delay in a general circuit is τ=iRinCi.

Let’s calculate the delay for an inverter driving n identical load inverters like on the drawing below.

How to calculate the delay in VLSI design using RC representation
RC representstion of the inverter driving n identical inverters

Here load is represented by capacitance 3nC, driving inverter is represented by the capacitance 3C. Then the total capacitance is 3C(1+n), and the delay is τ=3RC(1+n).

Usually it is comfortable to speak about delay in the non-process related terms normalising the delay to parasitic capacitance 3RC, so we have tdelay=τ3RC.

Educational content can also be reached via Reddit community r/ElectronicsEasy.