Embedded Systems

Embedded processors and architecture models

architecture processor

Embedded processors can be combined in a groups, architecture.  They vary by the processes they can execute. And if they can proceed the same machine code instructions, they do belong to the same architecture.

Instructure Set Architecture (ISA) are the features, built into the architecture, where operations and operands are defined for creating programs.  ISA also defines storage, interrupts and addressing models. These ISA characteristics are very important for performance, design time, and functionality of the embedded design. Architecture is based on several ISA models – application-specific ISA model, general-purpose ISA model, instruction-level parallel ISA model, and combination of these ISA models. ISA models will be considered further.

Application-specific ISA models are controlled model, datapath model, and finite state machine with datapath (FSMD) model. The last one include FPGAs and PLDs.

General-purpose ISA models are complex instruction set computing (CISC) model and reduced instruction set computing (RISC) model. CISC ISA based on a several simple operations that define complex operations. RISC ISA is based on the architecture with less amount of operations and instructions, and reduced number of cycles per operation. RISC processors have only one-cycle operations and CISC processors have multiple-cycle operations.

Instruction-level parallel ISA models can work with multiple operation in parallel. They can be ranged to single instruction multiple data model, superscalar machine model, very long instruction word computing (VLIWC) model.

Operations are several instructions, that execute certain commands. Different processors can execute the same operations with different amount of operations. These operations are functions for operating with data, including data computations, data movement from register to register, input and output operations, and content switching. Different processor can be characterised with similar set of operations, but they usually have different set of instructions, or operations may have different names, or operate differently.  ISA operations include math and logic operations, shift and rotate operations, load and store, comparing operations and others. Operation represented by a combination of bits, that referred to a operational code (opcode).

Operands are data sets, that operations work with. Different architectures operate with different data types and formats. In the ISA data types are defined as 8 bits, 16 bits and 32 bits, simple operand type, halfwords and words respectively. All the rest data types are based on these simple data types. Operand formats are binary, decimal and hexagonal.

Programmable storage is defined by the memory organisation. Memory here is the array of programmable storage for storing data. Arrays are having indices, that are referring to memory addresses of locations (units of memory). Address space is the set of physical or actual addresses. Address spaces can be:

    • linear, here address locations are incremental;
    • segmented. Here address portion is divided into segment. Memory location is defined by the segment identifier, that consist of segment number and offset. Segme3nt number is defined by a register. Offset consist of the base address and a limit. If the offset is lessor equal than limit, it is added to the base address.
    • containing address regions;
    • limited.

ISA can also define the way data is stored – the order of bits/bytes, or byte ordering. There is two byte-ordering techniques – big-endian and little-endian. Big-endian approach says where most significant byte is stored. Little-endian – where less significant byte stored.

Another way of memory organisation is defined by the register set. Register is type of memory, used to store operand for immediate use. The number of registers in a processor varies from several to hundreds.

Memory organisation can be defined by the way registers are used. Here different registers are used for different operations.

Processors can be divided by the data size of a memory space for addressing a single instruction. Usually processors support 4-bit, 8-bit, 16-bit, 32-bit and 64-bit processing.

Embedded processor can vary by their addressing modes, or the way they access operand storage – load-store architecture, .

Interrupts are ways to stop program flow in order to perform another set of code in case of specific event.

 

 

 

 

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