An embedded processor consists of CPU, memory, I/O, and busses. There are two models that describe CPU operation – von Neumann and Harvard architecture models. The difference between these two is memory. The picture below shows the differing memory approach in these two models.
The CPU is a processing unit responsible for three operations – fetching, decoding and executing instructions. CPUs consist of the following components – algorithmic logic unit, registers, control unit, and internal CPU buses.
An important part of the CPU is the CPU buses that interconnect components inside the CPU. These interconnects are wires, divided by logical functions.
Arithmetic logic functions perform mathematical and logical operations. Arithmetic logic function is accepting n-bit binary operations and perform logical, mathematical and comparison functions. An arithmetic logic function is characterised with one output and multiple inputs, and is a combinational logic circuit. It consists of a number of logic circuits called full adders.
Full adder is a logic circuit, combinational gate that performs adding operations. The full adder input is three 1-bit numbers (two operations and carry bit), and two output numbers (one sum result and carry bit).
Registers are the data spaces in the CPU that can be used for temporarily storing data or delaying signals. There are two types of registers – storage and shift registers. Storage registers are the fast programmable memory, that are used to temporarily store, modify or copy operations. This register is usually frequently accessed by the system. The Shift register is a CPU constituent, that delay signals passing the signals between various data spaces in the CPU.
Latches in the registers can be activated one by one, or simultaneously. These latches form the registers. The number of latches per register are characterized by the CPU.
Different ISAs use registers in primarily two ways to store data, that divide registers into two categories: general-purpose registers and special-purpose registers. General-purpose registers can operate and store any type of data. Special-purpose registers can perform only specific manipulations, act as flags, counters or I/O ports.
- Flags indicate that a certain event in a circuit has occurred;
- Counters make incrementing or decrementing functions asynchronously or synchronously. Synchronous counting occurs only when registers are connected to the common clock;
Controlling registers are usually responsible for generating timing signals, and actions like controlling fetching, decoding and executing operations.
In order to keep all processes in the processor synchronised, a system clock is used, which is an oscillator, producing a series of square waves with a fixed frequency. A system clock frequency is usually aligned with the slowest component on the board.
Embedded processors are characterised with the memory hierarchy – different memory types by size, speed and usage.
ROM (Read Only Memory) on-chip memory, is a memory type integrated into the processor, storing data that should remain even when the system is off. It is a non–volatile memory. The example of ROM structure, called ROM matrix, is depicted in the figure below.
Every intersection of the row and column is a memory cell. Bipolar and MOSFET memory cells are depicted below.
When the programmable link is in place, the transistor is biased ON, the memory cell is storing «1», when the programmable link is broken – «0». ROM type makes a difference to how the programmable link is broken:
- MROM – can not be modified;
- PROM (programmable ROM), or OTP (one-time programmable) – can be one-time programmable;
- EPROM (erasable programmable ROM) – can be erased and reprogrammed selectively;
- EEPROM (electrically erasable and programmable ROM) – can be erased and reprogrammed more than once. The processor defines how many times data across the memory can be erased and reprogrammed.
MOSFET memory cell
BJT memory cell
ROM memory cell
RAM (Random-Access Memory) on-chip memory – usually main memory. Here any location can be accessed directly and content can be changed more than once. RAM is a volatile type of memory and its content can be erased when RAM is off. RAM can be static (SRAM) and dynamic (DRAM) types.
SRAM is a transistor–based memory type. DRAM is a capacitor–based memory type. SRAM memory uses less energy than DRAM, and DRAM is cheaper due to its capacitor model.
How SRAM memory cell look like
How DRAM memory cell looks like
Capacitors in DRAM can not hold data long enough. They are characterised by discharge, changes with time, and energy dissipation. DRAM requires a constant source of energy to refresh it and maintain the data flow. Data from DRAM is usually read before it is discharged. A sense amplification circuit senses the charge stored in the memory cell. Reading processes also discharges DRAM. That is why DRAM usually has a memory controller that controls the charging and discharging processes.
DRAM memory is usually considered as the main memory. It is used for large amounts of data – for a video, cache, and display. SRAM memory is usually used for small amounts of data, used in an external cache.
Cache memory takes place between the main memory and the CPU. Cache memory can exist integrated on-chip or external. When integrated on-chip it is called level-1 Cache. SRAM memory is usually used as level-1 cache. Cache memory is usually used to access pieces of main memory.
There are strategies of reading and writing data between level-1 cache and the main memory. Usually it occurs with single-word or multiple word blocks. Blocks are memory data and its location.
When a CPU reads the cache to get data, it is called cache hit. The reading process is then complete. If reading data is absent at the on-chip cache, it is called cache missed. Then off-chip cache is checked for data. If it is still missing, the main memory is accessed to obtain the data.
Data stored in cache can be:
- Set associative, where memory is divived into sets;
- Direct mapped, data is located by its associated block address;
- Full associative, data blocks are randomly placed in a memory.