LearningYear 2

Year 2: digital system design level 2

Module aims

The objective of this module is to empower students with the skills needed to employ organised digital system design techniques, hardware description languages, and verification tools for creating digital systems. Furthermore, the module will familiarise students with real-world implementation challenges encountered in digital system development.

A pre-requisite to this module is the year 1 digital system design level 1 module.

Module content

To achieve this, the module will cover the following content:

  • Digital system design process, EDA tools and design viewpoints, behavioural, dataflow, and gate-level descriptions
  • Hardware description languages, VHDL modelling concepts, behavioural and structural architecture descriptions, concurrent and sequential statements, and event-driven simulation
  • Building blocks for digital systems such as tri-state buffers, multiplexers, latches, flip-flops, registers, counters, arithmetic circuits, finite-state machines
  • Design methodology, synchronous systems, top-down design, register-transfer-level design, test benches, synthesis from VHDL
  • Implementation issues such gate delays, timing, critical path, communication between unsynchronised machines, and coping with metastability.
  • Introduction to Programmable Logic Devices (FPGAs, CPLDs)

Module delivery

This module will typically be majority delivered via lectures, but also supported by practical classes and workshops, as well as tutorials.

Module outcomes

Upon completion of the course, students will be able to:

  • Anticipate the performance of a component defined through a Hardware Description Language (VHDL).
  • Create VHDL representations for digital data-path components, finite state machines, and algorithmic state machines.
  • Devise and execute basic synchronous digital systems using FPGA hardware.
  • Determine the timing constraints and performance boundaries of a given digital circuit.